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Several Precise Timing Programming Methods of Single Chip Microcomputer Timing Interrupt

The interrupt response delay time of MCS-51 single-chip microcomputer depends on whether other interrupt service routines are in progress, or on what kind of instructions are being executed.The interrupt response time in a single interrupt system is 3 to 8 machine cycles[1]. Regardless of the cause of the error, in precise timing applications, their influence must be considered to ensure precise timing control. According to the different application situations of the timing interrupt, different precise timing programming methods should be selected.

Introduction: The interrupt response delay time of MCS-51 single-chip microcomputer depends on whether other interrupt service routines are in progress, or on what kind of instructions are being executed.The interrupt response time in a single interrupt system is 3 to 8 machine cycles[1]. Regardless of the cause of the error, in precise timing applications, their influence must be considered to ensure precise timing control. According to the different application situations of the timing interrupt, different precise timing programming methods should be selected.

In this article, the timer T1 works in timing mode 1 as an example, and the crystal oscillator frequency is 12MHz.

1 Method 1

When the timer overflow interrupt is responded to, stop the timer counting, read the count value (reflecting the delay time of the interrupt response), and calculate how long it will take until the next interruption based on this count value to reload and Start the timer. For example, if the timing period is 1ms, the reload value of the timer is usually -1000 (0FC18H). The following program considers the 7 machine cycle time from the stop count (CLR TR1) to the restart count (SETB TR1) when calculating the precise reload value for each timing period. In the program, #LOW(-1000+7) and #HIGH(-1000+7) are assembly symbols, which respectively represent the low byte (1FH) and high byte (0FCH) of the immediate value -1000+7=0FC1FH.

CLR EA; disable all interrupts
CLR TR1; stop timer T1
MOV A, #LOW(-1000+7); the low byte of the expected number
ADD A, TL1; make corrections
MOV TL1, A; reload low byte
MOV A, #HIGH(-1000+7); processing the high byte
ADDC A, TH1
MOV TH1, A
SETB TR1; restart the timer
SETB EA; restart interrupt

This method is suitable for timing errors caused by various reasons and is a general method.

2 Method 2

If the timing period is 10ms, usually the timer reload value is 0D8F0H, and the interrupt subroutine is as follows[2]:
ORL TL1, #0F0H
MOV TH1, #0D8H

Here use ORL TL1, #0F0H instead of MOV TL1, #0F0H can improve timing accuracy. This method is only applicable when the lower 4 bits of the lower byte of the reload value are zero, and the interrupt response delay time is less than 16 machine cycles. Similar timer reload values ​​are 0FFF0H, 0FFE0H, etc.

3 Method 3

If the timing period is 1ms, usually the timer reload value is 0FC18H, and the interrupt subroutine is as follows:
MOV A, #LOW(-1000+4); the low byte of the expected number
ADD A, TL1
MOV TL1, A
MOV A, #HIGH(-1000+4); processing the high byte
ADDC A, TH1
MOV TH1, A
DEC TL1; restore 2 machine cycles ahead of schedule

In this method, the timer counting process is not stopped. If the instruction ADDC A, TH1 or MOV TH1, A happens to occur when TL1 overflows to carry into TH1, the value of TH1 is wrong, which will cause greater errors. . For this reason, the beginning of the program segment is the reload value plus 4, if there is an overflow carry, it can happen in advance, of which 2 machine cycles are taken into account for the time occupied by TL1 reloading.

This method is suitable for situations where there are no other higher priority interrupt sources in the system. If it is similar to method 1, adding the prohibition of all interrupts (CLR EA) and the opening of interrupts (SETB EA) instructions at the beginning and end of the block respectively, it will be applicable to all situations.

4 Method 4

If the timing period is uncertain, it is only known that the timer reload value is stored in registers R3 and R2. The interrupt subroutine is as follows:
MOV A, #05H; 3 machine cycles to load TL1, 2 cycles in advance
ADD A, TL1
ADD A, R2
MOV TL1, A
MOV A, R3; processing high byte
ADDC A, TH1
MOV TH1, A
DEC TL1; restore 2 machine cycles ahead of schedule

This method is suitable for the situation where the timing period is uncertain, and the others are the same as method 3.

5 Method 5

When the location of the timing interrupt is predictable, it usually appears at the AJMP $ (or SJMP $) waiting instruction of the main program, and the interrupt delay time is 3 or 4 machine cycles. A fixed value of 4 can simplify the compensation procedure. Taking the timing period of 1ms as an example, the interrupt subroutine is as follows:
ORG 001BH
MOV TL1, #LOW(-1000+4)
MOV TH1, #HIGH(-1000+4)

This method is suitable for the situation that timed interrupts always occur at the same instruction location and there are no other interrupt sources.

Concluding remarks

The errors of the above five methods are not more than 1 machine cycle, among which methods 1, 3, and 4 are more general and applicable to any situation, but the procedure is longer; methods 2 and 5 are simple, but they must be used only when they meet the corresponding conditions.Of course, there are other ways[3], But it is more cumbersome and not ideal, so I won’t introduce them one by one here.

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