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Method for Evaluating Phase Noise Using Distributed PLL Systems

For digital beamforming phased arrays, to generate local oscillators (LOs), a commonly considered implementation is to assign a common reference frequency to a series of phase-locked loops distributed in the antenna array. For these distributed phase-locked loops, methods for evaluating combined phase noise performance are currently not well documented in the literature.

In a distributed system, common noise sources are correlated, while distributed noise sources, if uncorrelated, degrade when RF signals are combined. This can be evaluated very intuitively for most components in the system. For a phase locked loop, each component in the loop has a noise transfer function associated with it, and their contribution is a function of the control loop as well as any frequency transitions. This adds complexity when trying to evaluate the combined phase noise output. In this paper, a method for tracking distributed PLL contributions at different frequency offsets is proposed, based on known PLL modeling methods, and an evaluation of correlated and uncorrelated contributing factors.

As with any radio system, the implementation of LO generation needs to be carefully designed for both the receiver and the exciter. As digital beamforming becomes more common in phased array antenna systems, the need to distribute the LO signal and reference frequency among a large number of distributed receivers and exciters complicates the design.

Trade-offs at the system architecture level include assigning the desired LO frequency or assigning a lower frequency reference, and generating the desired LO at a physical location close to the point of use. Locally generating the LO via a phase locked loop is a highly integrated off-the-shelf option. The next challenge is to evaluate system-level phase noise from various distributed components as well as centralized components.

A system using a distributed phase-locked loop is shown in Figure 1. The common reference frequency is distributed to multiple phase-locked loops, each producing an output frequency. The LO output in Figure 1a is assumed to be the LO input of the mixer of Figure 1b.

Method for Evaluating Phase Noise Using Distributed PLL Systems
Figure 1. Distributed phase-locked loop system. Each oscillator is phase locked to a common reference oscillator. The LO signals from 1 to N are applied to the LO ports of the mixers shown in the phased array.

A challenge for system designers is tracking the noise contribution of a distributed system, understanding correlated and uncorrelated noise sources, and estimating the overall system noise. In a phase-locked loop, this challenge becomes even more severe because the noise transfer function is a function of the frequency translation in the phase-locked loop and the setting of the loop bandwidth.

Motivation: Combined PLL Measurement Example

Figure 2 shows an example measurement for a combined phase-locked loop. These data are obtained by combining transmit outputs from multiple ADRV9009 transceivers. The figure shows the case of a single IC, two combined ICs, and four combined ICs. For this dataset, a clear 10logN improvement can be seen after IC combination. To achieve this result, a low noise crystal oscillator reference is required. The motivation for the modeling in the next section is to derive a method to compute in a large array with many distributed transceivers, and more generally any architecture with a distributed phase-locked loop, this measurement would How to change.

Method for Evaluating Phase Noise Using Distributed PLL Systems
Figure 2. Phase noise measurement of two combined phase-locked loops.

Phase Locked Loop Model

Noise modeling in phase locked loops is well documented. 1-5 Figure 3 shows the output phase noise plot. In this type of plot, the designer can quickly assess the noise contribution of each component in the loop, and these contributions add up to determine the overall noise performance. The model parameters were set to represent the data shown in Figure 2, and the source oscillator was used to estimate phase noise when a large number of ICs were grouped together.

Method for Evaluating Phase Noise Using Distributed PLL Systems
Figure 3. Typical phase-locked loop phase noise analysis showing noise contributions from all components. Total noise is the sum of all contributing factors.

To examine the effect of the distributed phase-locked loop, first derive the reference contribution and the contributions of the remaining PLL components from the PLL model.

Extend a known PLL model to a distributed PLL model

This section describes the procedure for calculating combined phase noise for systems with multiple distributed phase-locked loops. The premise of this approach is the ability to separate the noise contribution of the reference oscillator from the noise contribution of the VCO and loop components. Figure 4 shows a hypothetical distributed example where one reference oscillator corresponds to multiple PLLs. This calculation assumes a noise-free distribution, which is impractical, but serves to illustrate the principle. The noise contributions of distributed PLLs are assumed to be uncorrelated and reduced by 10logN, where N is the number of distributed PLLs. As the channel increases, the noise improves at larger offset frequencies, and for large distributed systems, the noise becomes almost entirely dominated by the reference oscillator.

Method for Evaluating Phase Noise Using Distributed PLL Systems
Figure 4. Getting started with the distributed phase-locked loop phase noise modeling approach: Extracting the phase noise contributions of the reference oscillator and all other components in the phase-locked loop except the reference oscillator from the phase-locked loop model. As a function of the number of distributed PLLs, the combined phase noise assumes that the reference noise is correlated, while the noise contributions distributed among multiple PLLs are uncorrelated.

The example shown in Figure 4 simplifies assumptions about the reference oscillator distribution. In a true system analysis, the system designer should also consider noise contributions in the reference oscillator distribution, which degrade the overall result. However, simplified analysis like this can be very useful to understand how architectural trade-offs can affect the overall phase noise performance of the system. Next we look at the effects of phase noise in distributed systems.

Description of Phase Noise in Reference Distributions

This section evaluates two examples of distribution options. The first case considered is shown in Figure 5. In this example, a wideband PLL, which is often used to quickly tune the VCO frequency, was chosen. The distribution of the reference signal is accomplished with a clock PLL IC, which is also commonly used to simplify timing constraints on digital data links such as JESD interfaces. The individual contributing factors are shown in the lower left corner. These contributors are at the frequency of the device and are not adjusted to the output frequency. The phase noise plot in the lower right corner shows the system-level phase noise for different numbers of distributed PLLs.

Method for Evaluating Phase Noise Using Distributed PLL Systems
Figure 5. Distributed wideband PLL with PLL IC in the distribution.

Some features of this model are worth noting. Assuming a high performance crystal oscillator with a nominal frequency of 100 MHz, the single contribution of the central oscillator is reflected in the higher end crystal oscillators available, although not necessarily the best and most expensive option available. While the central oscillator output actually fans out to a limited number of distributed PLLs, these PLLs again fan out and repeat by some practical limit to achieve full distribution in the system. For the distribution contribution in this example, assume there are 16 distribution components and then assume they will fan out again. The single contribution of the distributed circuit shown in the lower left corner is the noise of the PLL components without the contribution of the reference oscillator. The distribution in this example assumes the same frequency as the source oscillator, and the noise contributor is chosen based on the typical IC available for the function.

The wideband PLL assumes the S-band nominal frequency and is set to use a 1 MHz loop bandwidth (as wide as the actual loop bandwidth as possible) for fast tuning.

It is worth noting that these models were chosen to be representative of possible real-world scenarios and to account for cumulative effects in the array. It is expected that any detailed design might improve a particular PLL noise profile, and this analysis method is intended to aid in engineering decisions about where to allocate design resources for the best overall performance, not In order to make exact inferences relative to the available components.

The plot in the lower right corner of Figure 5 calculates the total combined phase noise of the LO distribution. The PLL noise transfer functions for each contributing factor are applied, which are adjusted to the output frequency and also include the effect of the PLL loop bandwidth. The number of systems is also included and assumed to be uncorrelated, so this contribution is reduced by 10logN. Assuming that the number of distributions is 16, the distribution contribution is reduced by 10log16 as previously described. In practice, this contribution decreases further as the distribution repeats itself. However, the additional noise contribution is less significant. For fan-out distributions in large arrays, the noise will be dominated by the first group of active devices. With 16 sets of fan-out, if each active device is an input to 16 other active devices, the additional distribution layer for 16 devices would only degrade ~0.25 dB with all devices uncorrelated with each other . If this distribution continues, the overall contribution will be smaller. Therefore, to simplify the analysis, this effect is not considered and the noise contribution of the distribution is calculated by computing the first 16 parallel distribution components.

The resulting curves illustrate several effects. Similar to the single PLL model, the near-carrier noise is dominated by the reference frequency, the far-carrier noise is dominated by the VCO, and far-carrier noise is improved when uncorrelated VCOs are combined. This is fairly intuitive. Less intuitively, the value of the model is heavily weighted in the frequency of offsets dominated by choices in the distribution. This result leads to considering a second example with a lower noise profile and a narrower PLL loop bandwidth.

Figure 6 shows a different approach. Use the same low noise crystal oscillator as a reference. But it is distributed through the RF amplifier, not through PLL retiming and resynchronization. Choose a fixed frequency distributed PLL. This has two effects: With a single frequency and a narrow tuning range, the VCO can be inherently better, and the loop bandwidth can become narrower. The figure in the lower left corner shows the individual contributing factors. The central oscillator is the same as in the previous example. Note the distribution amplifiers: when considering low phase noise amplifiers, their performance is not particularly high, but much better than using a PLL LC (as in the previous example). With a better VCO and a narrower loop bandwidth, the distributed PLL improves at higher offset frequencies, but is actually worse than the wideband PLL example at an intermediate frequency of ~1 kHz. The lower right corner shows the combined result: the reference oscillator dominates the low frequencies, while above the loop bandwidth, the performance is dominated by the distributed PLLs and increases with the array size and number of distributed PLLs.

Method for Evaluating Phase Noise Using Distributed PLL Systems
Figure 6. Distributed narrowband PLL with amplifiers in the distribution.

Figure 7 shows a comparison between these two examples. Note the wide range of differences in the ~2 kHz to 5 kHz offset frequency range.

Method for Evaluating Phase Noise Using Distributed PLL Systems
Figure 7. Comparison between Figures 5 and 6, showing the wide range of system-level performance based on the chosen distribution and architecture.

Distributed PLL Array Level Considerations

Based on an understanding of the weighted contribution to the overall system phase noise performance, several conclusions can be drawn regarding phased array or multi-channel RF system architectures.

PLL bandwidth

Traditional PLL designs optimized for phase noise set the loop bandwidth to the offset frequency to minimize the overall phase noise profile. The frequency at this point is typically the frequency at which the reference oscillator phase noise, normalized to the output frequency, intersects the VCO phase noise. For distributed systems with multiple PLLs, this may not be the optimal loop bandwidth. The number of distributed components also needs to be considered.

To obtain optimal LO noise in a system implemented with a distributed phase-locked loop, a narrower loop bandwidth is required to minimize the reference oscillator-related noise contribution.

For systems that need to quickly tune the PLL, the loop bandwidth is often expanded to optimize speed. Unfortunately, this idea of ‚Äč‚Äčoptimizing the distributed phase noise contribution is itself counter-intuitive. One of the options to overcome this problem is to place a distributed narrow-band cleanup loop before the wide-band loop to reduce the offset frequency of reference noise and distributed noise-related locations.

large array

For systems using thousands of channels, if the contributions of distributed components remain uncorrelated, the system can be greatly improved. The main considerations may revolve around the choice of reference oscillator and maintaining a low-noise distributed system for distributed receivers and exciters.

direct sampling system

With the increasing popularity of GSPS converters with increasing speed and RF input bandwidth, direct sampling systems are gradually being implemented at microwave frequencies. This leads to an interesting trade-off. The data converter only needs one clock frequency, and the RF tuning is done entirely in the digital domain. By limiting the tuning range, it is possible to build a VCO with higher phase noise performance. This also reduces the loop bandwidth of the PLL that creates the data converter clock. A lower loop bandwidth reduces the noise transfer function of the reference oscillator to a lower offset frequency, thereby reducing its contribution to the system. This, combined with an improved VCO, may in some cases benefit distributed systems, even though single-channel comparisons seem to favor alternative architectures.

Component options

Depending on the choices required in the system architecture, the designer has a large number of component options available. The updated version of the 2018 RF, Microwave and Millimeter Wave Product Selection Guide has been released, and those who need it can click “Read the original text” to get it for free.

Integrated VCO/PLL options include the ADF4371/ADF4372. They offer output frequencies up to 32 GHz and 16 GHz, respectively, with an advanced PLL phase noise FOM of C234 dBc/Hz. The ADF5610 provides outputs up to 15 GHz. The output of the ADF5355/ADF5356 can reach 13.6 GHz and the output of the ADF4356 can reach 6.8 GHz.

For separate PLL and VCO configurations, the ADF41513 operates up to 26 GHz and features an advanced phase-locked loop phase noise FOM of -234dBc/Hz. Sometimes a consideration when choosing a PLL IC is to operate the phase detector at the highest possible frequency, from multiplying 20logN to the output frequency, to minimize noise in the loop. The HMC440, HMC4069, HMC698 and HMC699 employ PFDs operating at frequencies up to 1.3 GHz. For VCOs, the 2018 selection guide lists dozens of VCO options ranging from 2 GHz to 26 GHz.

For the direct sampling option, both ADC and DAC are released. The product supports direct sampling in L-band and S-band. The ADC has a higher input frequency bandwidth and supports C-band direct sampling. The AD9208 is a dual 3 GSPS ADC with an input frequency of 9 Ghz that supports sampling in the upper Nyquist region. The AD9213 is a single-channel 10 GSPS ADC that supports receivers with large instantaneous bandwidth. For the DACs, the AD917x family uses a dual 12 GSPS DAC and the AD916x family uses a single 12 GSPS DAC, optimized for lower residual phase noise and better SFDR. Both series support L-band and S-band waveform generation.

PS. This section only provides getting started guide.


This article describes a method for evaluating phase noise for systems employing distributed phase-locked loops. The premise of this approach is that each component can be tracked by its individual noise, the noise transfer function between the component and the system output, the quantities used, and any correlations between the devices. The examples shown are not intended to make assertions about available components or architectural capabilities. They are intended to illustrate a method to help designers in digital beamforming phased arrays, array-level phase noise contributors in LOs, and clock distribution networks serving distributed waveform generators and receivers. evaluation of.

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