“SAR ADCs are a very common topology, a compromise that provides a good balance between speed, resolution, and power. A key advantage of SAR ADCs is that there is virtually no delay. Therefore, the use of SAR ADCs can be seen in many application areas.

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SAR ADCs are a very common topology, a compromise that provides a good balance between speed, resolution, and power. A key advantage of SAR ADCs is that there is virtually no delay. Therefore, the use of SAR ADCs can be seen in many application areas.

This article will introduce the principle of SAR ADC and some points that need to be paid attention to in the design of SAR ADC driving circuit.

**SAR ADC Principle**

SAR ADC (Successive Approximation Register), namely successive approximation ADC.

As shown in the figure below, the SAR ADC is mainly divided into four parts: sample and hold circuit, analog comparator, SAR successive approximation register and DAC digital-to-analog converter.

Figure 1: Typical topology of a SAR ADC

There are two main stages in the working process of SAR ADC: sampling stage and conversion stage.

**Sampling stage:**

In the sampling stage, the switch S2 is turned off and the switch S1 is turned on, and the ADC sampling capacitor C is charged at this time.

Figure 2: Sampling stage of a SAR ADC

**Conversion stage:**

During the conversion phase, switch S1 is open and switch S2 is closed.

Figure 3: Transformation Stage

The following figure is a 6-bit ADC conversion process:

The voltage on the sampling capacitor is compared with the voltage on the internal DAC through the comparator, from high to low, step by step.

The successive approximation register provides additional code to the internal DAC on each clock cycle.

If the analog voltage on the sampling capacitor is higher than the internal DAC voltage, it is recorded as 1

If the analog voltage on the sampling capacitor is higher than the internal DAC voltage, it is recorded as 0

Figure 4: Conversion process of 6-bit ADC

So, conversion time is conversion dependent on clock frequency and ADC resolution. In the example above, the conversion takes 6 clock cycles to get the result. After converting, most ADCs return to the sampling phase.

**SAR ADC driver circuit design**

Why do you need a driver circuit?

In general, the input structure of the SAR ADC is a switched capacitor sampling circuit. The charging and discharging of the capacitor requires sufficient current to support it. At the same time, due to the existence of capacitance and some on-chip parasitic capacitance of the switch itself, some charges will be injected into the power supply in reverse, which is called charge injection kickback, which will cause oscillation.

Figure 5: Switched capacitor sampling circuit, charge injection kickback (Image credit: ADI)

As shown above: when the switch is closed, sampling; when the switch is open, conversion. Whenever the switch is closed, the charge present in the capacitor itself is injected back into the sensor, causing oscillation. We need additional settling time to remove this part of the disturbance.

To power the SAR ADC and reduce the effects of charge kickback. Generally, we will add an ADC driver circuit (amplifier) and a switched sampling capacitor charging RC circuit between the sensor and the SAR ADC.

Figure 6: SAR ADC driver circuit design (Image source: ADI)

**Switched sampling capacitor charging RC circuit**

The role of the RC is to reduce the effects of charge kickback and limit broadband noise. This requirement imposes further constraints on amplifier selection and performance.

In order to choose the appropriate RC resistance and capacitance, we must ensure at least the following two points:

First, make sure that the chosen ADC driver and RC circuit can actually drive the ADC. That is to say, the resistance value of the RC circuit should not be too large. Whether it can drive the ADC enough is determined by the input current required by the ADC, that is, the input resistance of the ADC.

Second, make sure that the voltage on the sampling capacitor is as close to the input voltage as possible. Before the conversion stage, make sure that the voltage on the sampling capacitor is as close to the input voltage as possible and settles to the desired resolution.

As shown in the figure below, in the SAR ADC sampling stage, S1 is turned off, and the input voltage Vin charges the sampling capacitor C through the resistor R. The voltage difference between the voltage across the sampling capacitor and the input voltage should be less than half the LSB (least significant bit).

Figure 7: Voltage on Sampling Capacitor

Next we look at the calculation of the time constant τ.

The voltage Vc on the sampling capacitor as a function of time:

If only the ADC sampling circuit structure is considered, the time constant t depends on the internal sampling capacitor C and the switch resistance R. The time constant t is equal to R times C.

where FSR is the full-scale range and N is the number of bits in the ADC.

For different resolutions, the table below shows how many time constants are required at least to keep the error within 1 LSB.

For example, an 8-bit ADC needs at least 6 times the time constant to ensure that the error is within 1 LSB.

The derivation and calculation process will not be expanded here. If you are interested, you can read the following ADI article: Front-end amplifier and RC filter design of precision SAR analog-to-digital converters

When there is an external RC circuit, the time constant τ needs to be calculated by considering the RC in the structure of the external RC circuit and the internal ADC sampling circuit and other existing parasitic impedance parameters. No discussion here.

To select the appropriate resistors and capacitors for an RC circuit, visit the appropriate Digi-Key product webpage.

Digi-Key Resistors

Digi-Key Capacitors

**ADC driver circuit (amplifier)**

When choosing the drive circuit (amplifier), we need to pay attention to the following two points:

The amplifier should support charge current and be able to absorb charge injection kickback.

The output of this amplifier needs to be completely stable at the end of the sampling edge so that the ADC input is sampled without adding error.

This means that the amplifier should be able to provide instantaneous current steps and the corresponding amplifier should have a high slew rate. To provide fast settling response to these transient events, the corresponding amplifier should have high bandwidth.

When selecting an amplifier, you can filter by parameters such as slew rate and bandwidth. Through the Digi-Key website, it is easy to select the appropriate amplifier according to the parameters.

**Digi-Key Amplifier**

Figure 8: Amplifier parameter options on the Digi-Key website

**Selection of SAR ADC**

Choosing a suitable SAR ADC can greatly reduce the requirements for the driving circuit and simplify the design of the driving circuit. You can make a quick selection through the Digi-Key website.

Digi-Key SAR ADCs

From the perspective of SAR ADC driver circuit design, we need to pay attention to the following two points:

**long sampling phase**

A longer sampling period reduces the settling requirements for the driver amplifier and allows for a lower cut-off frequency of the RC circuit, which means higher noise and/or lower power/bandwidth amplifiers can be used. Larger values of R and smaller corresponding values of C can be used in RC circuits, reducing amplifier stability issues without significantly impacting distortion performance. A larger value of R helps protect the ADC input from overvoltage conditions; it also reduces dynamic power dissipation in the amplifier.

**High Input Impedance SAR ADC:**

The advantage of high input impedance is that at slow (

Let’s take the ADI AD4000 as an example. The AD4000 supports a high-impedance input mode, which reduces input current requirements and can be driven with a much higher source impedance than traditional SARs. This means that the resistor value in the RC circuit can be 10 times larger than in conventional SAR designs.

Figure 9: Effect of AD4000 High Impedance Mode and Normal Mode on Input Current (Image Source: ADI)

In slow applications (signal bandwidth precision ADC driver design tool

If you think the above SAR ADC driver design is cumbersome, you can also use the ADI precision ADC driver design tool. By doing this, you can simulate simulations based on different parameters, reducing the time required to design a precision ADC driver.

Figure 10: ADI Precision ADC Driver Design Tool (Image source: ADI)

**Summary of this article**

SAR ADC is a very common topology. Driving circuit design is often a difficult point in SAR ADC design. Understand SAR ADC principles. For SAR ADC, RC circuit, drive circuit (amplifier), we often need to put them together for comprehensive consideration. Knowing the design points of each part and using the appropriate tools can often do more with less.

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