Breaking News

Embedded Hardware Communication Interface Protocol – IIC (1): Protocol Basics

This section continues to talk about another serial communication interface-IIC in the embedded hardware communication interface protocol. Compared with the UART serial port protocol and the SPI serial peripheral interface protocol, this IIC has its own unique features.

This section continues to talk about another serial communication interface-IIC in the embedded hardware communication interface protocol. Compared with the UART serial port protocol and the SPI serial peripheral interface protocol, this IIC has its own unique features.

Introduction

IIC (Inter-Integrated Circuit), integrated circuit bus.

IIC stands for Inter-Integrated Circuit (Integrated Circuit Bus). This type of bus is a simple, bidirectional, two-wire, synchronous serial bus designed by Philips Semiconductors in the early 1980s. It is mainly used to connect the overall circuit ( ICS), IIC is a multi-directional control bus, which means that multiple chips can be connected to the same bus structure, and each chip can be used as a control source for real-time data transmission. This approach simplifies the signal transmission bus interface.

Compared with the SPI interface “Embedded Hardware Communication Interface Protocol – SPI (1) Protocol Foundation”, the IIC interface here defines a multi-master and multi-slave communication architecture, and there can be multiple hosts and multiple slaves on the same IIC bus. machine. The “master->slave” communication architecture makes the communication initiative on the host side, the host initiates a communication, and the slave responds.

signal line

The IIC acts as a two-wire serial bus, and the signal lines are:

SCL (Serial ClockLine): serial clock, host output

SDA (Serial DataLine): serial data, bidirectional transmission

The level of the bus signal is connected to the circuit, and a pull-up resistor Rp is generally added, so that when the bus is idle, the signal pin is in a high-level state.

Here can be specific to the manuals of some chips, and clearly write the pull-up resistor requirements when the line is connected:

Pull-up resistors required by the SHT20 temperature and humidity sensor:

  

Embedded Hardware Communication Interface Protocol – IIC (1): Protocol Basics

In the touch key BS116A-3 chip data sheet:

  

Embedded Hardware Communication Interface Protocol – IIC (1): Protocol Basics

Signal timing

As a synchronous serial bus, IIC can be considered to have two synchronization signals. The first is the communication start and end flags, which tell the slave device hanging on the IIC bus when to start communication and when to end; the second is The synchronous clock signal SCL is output and sampled bit-by-bit based on the transition of the SCL when the sender and receiver interact with each other.

  

Embedded Hardware Communication Interface Protocol – IIC (1): Protocol Basics

start sign

In the idle state, both SCL and SDA are high. At a certain moment, when SDA is pulled low, the IIC transmission is considered to be started at this moment.

end sign

When the data transfer is about to be completed, when SCL is at a high level, SDA is forced to be pulled high, and the IIC transfer is considered to end at this moment.

data output

When SCL is low, the sender changes the level of SDA bit by bit according to the content of the transmitted data.

data sampling

When SCL is high, the receiver reads the level of SDA and receives it bit by bit, and 8 bits form a Byte.

ACK

ACK indicates that SDA remains low during the high level of the ninth clock after 8bit data.

Answer NACK

NACK indicates that SDA remains high during the high level of the ninth clock after 8bit data.

For comprehension and memory, group memory is recommended:

When SCL is high, SDA is pulled low to start, and SDA is pulled high to end;

When SCL is high, the receiver samples the SDA pin level; when SCL is low, the sender changes the SDA pin level;

Acknowledge bit, SDA low level means ACK, SDA high level means NACK.

The above are the signal timing state characteristics that may appear in the IIC communication process.

If we want to compare it with the SPI interface, we find that there are multiple slave devices on the IIC bus, and when a host wants to communicate with a slave device at a certain time, it does not have a single chip select signal pin SS like SPI. .

Then, in order to realize the communication between the host and the designated slave, the host will first send the address of the designated slave device through the interface every time the communication starts. In this way, the corresponding slave device can be selected, and the follow-up can be carried out. communication operations.

Similarly, each peripheral device with an IIC interface has the address configuration in its data sheet:

SHT20 temperature and humidity chip address configuration:

  

Embedded Hardware Communication Interface Protocol – IIC (1): Protocol Basics

BS116-3 touch chip address configuration:

  

Embedded Hardware Communication Interface Protocol – IIC (1): Protocol Basics

AT24C1024B memory chip:

Embedded Hardware Communication Interface Protocol – IIC (1): Protocol Basics

  

Embedded Hardware Communication Interface Protocol – IIC (1): Protocol Basics

We found that the address of the IIC device is generally 7bit, and the data sent once is sent in a byte of 8bit, so when the address is to be sent, it will bring the read and write bits to form a byte and send it out.

The meaning of the read-write bit is mainly to clarify the IIC slave device, after being “named” by the host, whether it is read by the host or written by the host is judged by this read-write bit.

In addition, similar to the AT24C1024B memory chip, in the 7-bit address bit, there are 3 bits of A2, A1, A0 that can choose different connection methods on the hardware circuit, so there are 8 different slave addresses, that is It is said that 8 AT24C1024B memory chips of the same type can be hung on the same IIC bus.

interface configuration item

Compared with the rich configuration items of the SPI interface, the IIC has only 2 data lines, and the configurable is the toggle rate of the clock SCL, because the rate of this clock directly affects the data transmission rate.

The recommended value configured here should confirm the rate limit of each slave device on the IIC bus, so that when designing the IIC interface, the communication rate of all devices on the bus can be compatible.

SHT20 temperature and humidity sensor:

  

Embedded Hardware Communication Interface Protocol – IIC (1): Protocol Basics

BS116-3 touch chip clock limit:

  

Embedded Hardware Communication Interface Protocol – IIC (1): Protocol Basics

Clock requirements for AT24C1024B memory chip:

  

Embedded Hardware Communication Interface Protocol – IIC (1): Protocol Basics

To sum up, the IIC bus interface is a two-wire, multi-master and multi-slave, half-duplex communication interface protocol. Familiar with the timing diagram of the two signal lines, basically the understanding of IIC is almost the same.

The Links:   PM75CSD120 T640N14TOF